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Reset and hardware strapping timing

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NS9750B-A1 Datasheet 03/2006

Reset and hardware strapping timing

Reset and hardware strapping AC characteristics are measured with 10pF, unless otherwise noted.

Table 38 describes the values shown in the reset and hardware strapping timing diagram.

Note:

1 The hardware strapping pins are latched 5 clock cycles after reset_n is deasserted (goes high).

 R1: reset_n must be held low for a minimum of 10 x1_sys_osc clock cycles after power up.

 R2: reset_done is asserted 4ms after reset_n is driven high.

Parameter Description Min Max Unit Notes

R1 reset_n minimum time 10 x1_sys_osc clock cycles 1

R2 reset_n to reset_done 4 ms

Table 38: Reset and hardware strapping timing parameters

x1_sys_osc

reset_n

reset_done

1 2 ... 75 76 77 78 79 80 81 82 83 84 85 86 87 88

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