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PCI timing

64       

NS9750B-A1 Datasheet 03/2006

PCI burst write to NS9750B-A1 timing

PCI burst read to NS9750B-A1 timing

Note:

The functional timing for valid read data on

ad[31:0] is just an example. The actual response time

will depend on when the PCI bridge gets access to the AHB bus internal to NS9750B-A1.

pci_clk_out timing

pci_clk_in timing

3x pci_clk_in

P3P2

byte enablescmd

addr data0 data1 data2 data3 data4 data5 data6 data7

pci_clk_in

frame_n

ad[31:0]

cbe_n[3:0]

irdy_n

trdy_n

devsel_n

3x pci_clk_in

P3P2

P5P1P4P2

P3P2

byte enablescmd

addr data0 data1 data2 data3 data4 data5 data6 data7

pci_clk_in

frame_n

ad[31:0]

cbe_n[3:0]

irdy_n

trdy_n

devsel_n

P7P7P6P6

pci_clk_out

P10

P10P9P9

pci_clk_in

1 2 ... 63 64 65 66 67 68 69 70 71 72 73 ... 87 88

NS9750B-A1 Datasheet 1
Contents 3
NS9750B-A1 Datasheet 03/2006 4
NS9750B-A1 Features 5
2        6
System-level interfaces 8
System configuration 9
Table 2: PLL ND[4:0] 10
Pin name Configuration bits 10
General Purpose ID register 11
System boot 12
System Clock 13
NS9750B-A1 14
USB clock 15
System Memory interface 16
Pin # Signal Name 17
I/O Description 17
Name I/O Description 20
Ethernet interface 22
Clock generation/system pins 23
PCI interface 24
PCI/CardBus signals 26
24        28
GPIO MUX 29
Pin # Signal name 30
Table 12: GPIO MUX pinout 30
USB Power 35
Controller 35
CLSTN[0] 36
MLSTN[0] 36
CUSTN[0] 37
RED[0] 38
GREEN[0], BLUE[0] 38
C interface 39
USB Interface 39
Reserved pins 41
Address and register maps 42
BBus peripheral address map 43
Electrical characteristics 44
Maximum power dissipation 45
Typical power dissipation 45
DC electrical characteristics 46
USB DC electrical outputs 47
44        48
Power sequencing 49
Memory timing 50
SDRAM burst read (16-bit) 51
SDRAM burst write (16-bit) 52
SDRAM burst read (32-bit) 52
SDRAM burst write (32-bit) 53
SDRAM load mode 54
SDRAM refresh mode 54
Clock enable timing 54
SRAM timing 55
52        56
 WTWR = from 0 to 15 60
       57 61
58        62
Ethernet timing 63
Ethernet MII timing 64
Ethernet RMII timing 64
PCI timing 65
Internal PCI arbiter timing 66
64        68
C timing 69
LCD timing 70
68        72
LCD output timing 73
SPI timing 74
72        76
IEEE 1284 timing 77
USB timing 78
USB full speed load 79
USB low speed load 79
       80
JTAG timing 81
Clock timing 82
       79 83
Packaging 84
NS9750B-A1, 388 BGA 86
Product specifications 87

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Digi NS9750 Manuale Utente Pagina 68

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