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LCD timing
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67
Notes:
1 CLCDCLK is selected from 5 possible sources:
— lcdclk/2 (lcdclk is an external oscillator)
— AHB clock
— AHB clock/2
— AHB clock/4
— AHB clock/8
See the LCD chapter in the NS9750B-A1 Hardware Reference for acceptable clock frequencies for the
different display configurations.
2 The polarity of CLLP, CLFP, CLCP, and CLAC can be inverted using control fields in the LCDTiming1 register.
3 The CPL field in the LCDTiming2 register must also be programmed to T5-1 (see the LCD chapter in the
NS9750B-A1 Hardware Reference).
4 The PPL field in the LCDTiming0 register must also be programmed correctly (see the LCD chapter in the
NS9750B-A1 Hardware Reference).
5 These data widths are supported:
— 4-bit mono STN single panel
— 8-bit mono STN single panel
— 8-bit color STN single panel
— 4-bit mono STN dual panel (8 bits to LCD panel)
— 8-bit mono STN dual panel (16 bits to LCD panel)
— 8-bit color STN dual panel (16 bits to LCD panel)
— 24-bit TFT
— 18-bit TFT
6 See the LCD chapter in the NS9750B-A1 Hardware Reference for definitions of these bit fields.
7 Note that data is sampled by the LCD panel on the falling edge of the CLCP in “LCD output timing” on
page 69. If the polarity of
CLCP is inverted, this parameter is relative to CLCP falling.
8 C
load
= 10pf on all outputs.
9 CLCP high and low times specified as 50% of the clock period ±0.5ns.
10 Maximum allowable LCD panel clock frequency is 80 MHz.
L23 STN VSYNC active to HSYNC
inactive
LCDTiming0 STN color:
14+HSW+HFP
STN Mono8:
6+HSW+HFP
STN Mono4:
10+HSW+HFP
CLCP periods
L24 STN HSYNC inactive to VSYNC
inactive
LCDTiming0 HBP+1 CLCP periods
L25 STN VSYNC inactive to HSYNC
active
LCDTiming0 STN color: HFP+13
STN Mono8: HFP+15
STN Mono4: HFP+9
CLCP periods
L26 CLCP period 12.5 ns (min) ns
Parameter Description Register Value Units
Table 33: LCD timing parameters
- NS9750B-A1 Datasheet 1
- Contents 3
- NS9750B-A1 Datasheet 03/2006 4
- NS9750B-A1 Features 5
- 2 6
- System-level interfaces 8
- System configuration 9
- Table 2: PLL ND[4:0] 10
- Pin name Configuration bits 10
- General Purpose ID register 11
- System boot 12
- System Clock 13
- NS9750B-A1 14
- USB clock 15
- System Memory interface 16
- Pin # Signal Name 17
- I/O Description 17
- Name I/O Description 20
- Ethernet interface 22
- Clock generation/system pins 23
- PCI interface 24
- PCI/CardBus signals 26
- 24 28
- GPIO MUX 29
- Pin # Signal name 30
- Table 12: GPIO MUX pinout 30
- USB Power 35
- Controller 35
- CLSTN[0] 36
- MLSTN[0] 36
- CUSTN[0] 37
- RED[0] 38
- GREEN[0], BLUE[0] 38
- C interface 39
- USB Interface 39
- Reserved pins 41
- Address and register maps 42
- BBus peripheral address map 43
- Electrical characteristics 44
- Maximum power dissipation 45
- Typical power dissipation 45
- DC electrical characteristics 46
- USB DC electrical outputs 47
- 44 48
- Power sequencing 49
- Memory timing 50
- SDRAM burst read (16-bit) 51
- SDRAM burst write (16-bit) 52
- SDRAM burst read (32-bit) 52
- SDRAM burst write (32-bit) 53
- SDRAM load mode 54
- SDRAM refresh mode 54
- Clock enable timing 54
- SRAM timing 55
- 52 56
- WTWR = from 0 to 15 60
- 57 61
- 58 62
- Ethernet timing 63
- Ethernet MII timing 64
- Ethernet RMII timing 64
- PCI timing 65
- Internal PCI arbiter timing 66
- 64 68
- C timing 69
- LCD timing 70
- 68 72
- LCD output timing 73
- SPI timing 74
- 72 76
- IEEE 1284 timing 77
- USB timing 78
- USB full speed load 79
- USB low speed load 79
- 80
- JTAG timing 81
- Clock timing 82
- 79 83
- Packaging 84
- NS9750B-A1, 388 BGA 86
- Product specifications 87
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