Digi NS9750 Manuale Utente Pagina 7
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- Indice
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NS9750B-A1 Features
www.digi.com
3
Peripheral bus:
One 13-channel DMA engine supports USB
device
– 2 DMA channels support control
endpoint
– 11 DMA channels support 11 endpoints
One 12-channel DMA engine supports:
– 4 serial modules (8 DMA channels)
– 1284 parallel port (4 DMA channels)
All DMA channels support fly-by mode
External peripheral:
One 2-channel DMA engine supports
external peripheral connected to memory
bus
Each DMA channel supports memory-to-
memory transfers
Power management (patent pending)
Power save during normal operation
– Disables unused modules
Power save during sleep mode
– Sets memory controller to refresh
– Disables all modules except selected
wakeup modules
– Wakeup on valid packets or characters
Vector interrupt controller
Decreased bus traffic and rapid interrupt
service
Hardware interrupt prioritization
General purpose timers/counters
16 independent 16-bit or 32-bit
programmable timers or counters
– Each with an I/O pin
Mode selectable into:
– Internal timer mode
– External gated timer mode
– External event counter
Can be concatenated
Resolution to measure minute-range
events
Source clock selectable: internal clock or
external pulse event
Each can be individually enabled/disabled
System timers
Watchdog timer
System bus monitor timer
System bus arbiter timer
Peripheral bus monitor timer
General purpose I/O
50 programmable GPIO pins (muxed with
other functions)
Software-readable powerup status
registers for every pin for customer-
defined bootstrapping
External interrupts
4 external programmable interrupts
– Rising or falling edge-sensitive
– Low level- or high level-sensitive
Clock generator
On-chip phase locked loop (PLL)
Software programmable PLL parameters
Optional external oscillator
Separate PLL for USB
Operating grades/Ambient temperatures
200 MHz: 0 – 70° C
162 MHz: -40 – +85° C
125 MHz: 0 – 70° C
- NS9750B-A1 Datasheet 1
- Contents 3
- NS9750B-A1 Datasheet 03/2006 4
- NS9750B-A1 Features 5
- 2 6
- System-level interfaces 8
- System configuration 9
- Table 2: PLL ND[4:0] 10
- Pin name Configuration bits 10
- General Purpose ID register 11
- System boot 12
- System Clock 13
- NS9750B-A1 14
- USB clock 15
- System Memory interface 16
- Pin # Signal Name 17
- I/O Description 17
- Name I/O Description 20
- Ethernet interface 22
- Clock generation/system pins 23
- PCI interface 24
- PCI/CardBus signals 26
- 24 28
- GPIO MUX 29
- Pin # Signal name 30
- Table 12: GPIO MUX pinout 30
- USB Power 35
- Controller 35
- CLSTN[0] 36
- MLSTN[0] 36
- CUSTN[0] 37
- RED[0] 38
- GREEN[0], BLUE[0] 38
- C interface 39
- USB Interface 39
- Reserved pins 41
- Address and register maps 42
- BBus peripheral address map 43
- Electrical characteristics 44
- Maximum power dissipation 45
- Typical power dissipation 45
- DC electrical characteristics 46
- USB DC electrical outputs 47
- 44 48
- Power sequencing 49
- Memory timing 50
- SDRAM burst read (16-bit) 51
- SDRAM burst write (16-bit) 52
- SDRAM burst read (32-bit) 52
- SDRAM burst write (32-bit) 53
- SDRAM load mode 54
- SDRAM refresh mode 54
- Clock enable timing 54
- SRAM timing 55
- 52 56
- WTWR = from 0 to 15 60
- 57 61
- 58 62
- Ethernet timing 63
- Ethernet MII timing 64
- Ethernet RMII timing 64
- PCI timing 65
- Internal PCI arbiter timing 66
- 64 68
- C timing 69
- LCD timing 70
- 68 72
- LCD output timing 73
- SPI timing 74
- 72 76
- IEEE 1284 timing 77
- USB timing 78
- USB full speed load 79
- USB low speed load 79
- 80
- JTAG timing 81
- Clock timing 82
- 79 83
- Packaging 84
- NS9750B-A1, 388 BGA 86
- Product specifications 87
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